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| K4S643232E-TI/P CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Industrial Temperature Revision 1.2 October 2001 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P Revision History Revision 1.2 (October 24, 2001) * Removed CAS Latency 1 from the spec. CMOS SDRAM Revision 1.1 (August 7, 2001) - Target * Added CAS Latency 1 Revision 1.0 (January 12, 2000) * Final spec Revision 0.0 (December 20, 2000) - Preliminary Spec. * Initial draft -2- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES * * * * 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle(4K/64ms) CMOS SDRAM GENERAL DESCRIPTION The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * * * * * ORDERING INFORMATION Part NO. K4S643232E-TI/P60 K4S643232E-TI/P70 Max Freq. 166MHz 143MHz Interface LVTTL Package 86 TSOP(II) * Industrial Temperature range : -45oC to +85oC * - I/P : Industrial temperature (-45oC to +85oC) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 512K x 32 512K x 32 512K x 32 512K x 32 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. -3- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P PIN CONFIGURATION (Top view) CMOS SDRAM VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS 86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch) -4- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. CMOS SDRAM Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No connection on the device. CKE Clock enable A0 ~ A10 BA0,1 RAS CAS WE DQM0 ~ 3 DQ0 ~ 31 Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No Connection VDD/VSS VDDQ/VSSQ NC -5- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 CMOS SDRAM Unit V V C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS *Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -45oC to +85oC) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S643232E-60 is 3.135V ~ 3.6V CAPACITANCE Clock (VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min Max 4 4.5 4.5 6.5 Unit pF pF pF pF RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ31 -6- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P DC CHARACTERISTICS CMOS SDRAM (Recommended operating condition unless otherwise noted, TA = -45oC to +85oC, VIH(min)/VIL(max)=2.0V/0.8V) Parameter Symbol Test Condition CAS Latency 3 2 Speed -60 170 150 3 Unit Note -70 155 mA 150 mA 2 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 ICC2P ICC2PS ICC2N Burst Length =1 tRC tRC(min), tCC tCC(min), Io = 0mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable Io = 0 mA, Page Burst All bank Activated, tCCD = tCCD(min) tRC tRC(min) 2 20 mA 10 7 mA 5 55 mA 40 3 2 3 2 180 150 185 160 3 450 170 mA 150 165 mA 160 mA uA 4 5 3 2 Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N Active Standby Current in non power-down mode (One Bank Active) ICC3NS Operating Current (Burst Mode) ICC4 Refresh Current ICC5 Self Refresh Current ICC6 CKE 0.2V Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232E-TI** 5. K4S643232E-TP** -7- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = -45oC to +85oC) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 CMOS SDRAM Unit V V ns V 3.3V Vtt = 1.4V 1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50 50 30pF (Fig. 1) DC output load circuit Notes : 1. The VDD condition of K4S643232E-60 is 3.135V ~ 3.6V (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter CAS Latency CLK cycle time Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col.address delay Last data in to burst stop Col. address to col. address delay Mode Register Set cycle time Number of valid output data Symbol CL tCC(min) tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) tMRS(min) CAS Latency=3 CAS Latency=2 10 7 2 1 1 1 2 2 1 3 3 7 2 2 5 100 10 7 3 6 Version -60 2 10 2 3 3 7 2 2 5 3 7 -70 2 10 Unit CLK ns CLK CLK CLK CLK us CLK CLK CLK CLK CLK CLK ea 4 1 2 2 2 3 1 1 1 1 Note Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table. -8- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) 60 Version -60 12 18 18 42 100 70 -70 14 20 20 49 CMOS SDRAM Unit ns ns ns ns us ns 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CAS Latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 tSH tSLZ tSHZ tSS tCL CAS Latency=3 CAS Latency=2 tOH tCH tSAC Symbol Min CLK cycle time tCC 6 10 2 2.5 3 2.5 3 1.5 2.5 1 1 5.5 6 5.5 6 -60 Max 1000 Min 7 10 2 3 3 3 3 1.75 2.5 1 1 5.5 6 5.5 6 ns ns ns 3 2 ns 3 ns 3 ns ns 2 3 ns 1, 2 -70 Max 1000 ns 1 Unit Note Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. -9- Rev. 1.2 (Oct. 2001) K4S643232E-TI/P SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 CMOS SDRAM , A10/AP A9 ~ A0 Note H H X H L H X X L L L H L L H X L H L L H X H L L H H X H H X X OP code X 1,2 3 3 X X X V V X Row address L H Column address (A0 ~ A7) Column address (A0 ~ A7) 3 3 Bank active & row addr. Read & column address Write & column address Burst Stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable L L 4 4,5 4 4,5 6 H H H X X X L L L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V X X X V L H X V X L H X H L H L H L X X X X X X V X X 7 X H L L H H H H L X H L X H X H X H X (V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) - 10 Rev. 1.2 (Oct. 2001) K4S643232E-TI/P MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0 ~ BA1 RFU Function A10/AP RFU A9 W.B.L A8 TM A7 A6 A5 A4 CAS Latency A3 BT CMOS SDRAM A2 A1 Burst Length A0 Test Mode A8 0 0 1 1 A9 0 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved Length Burst Single Bit A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Write Burst Length Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Full Page Length : x32 (256) POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle. - 11 Rev. 1.2 (Oct. 2001) K4S643232E-TI/P BURST SEQUENCE (BURST LENGTH = 4) Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 Sequential 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 CMOS SDRAM Interleave 2 3 0 1 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 - 12 Rev. 1.2 (Oct. 2001) |
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